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1 november 1998 preliminary ml4801 variable feedforward pfc/pwm controller combo general description the ml4801 is a controller for power factor corrected, switched mode power supplies. key features of this combined pfc and pwm controller are low start-up and operating currents. power factor correction (pfc) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching fets, and results in a power supply that fully complies with iec1000-2-3 specifications. the ml4801 includes circuits for the implementation of a leading edge, average current boost type power factor correction and a trailing edge pulse width modulator (pwm). the pfc frequency of the ml4801 is automatically set at half that of the pwm frequency generated by the internal oscillator. this technique allows the user to design with smaller output components while maintaining the optimum operating frequency for the pfc. an over- voltage comparator shuts down the pfc section in the event of a sudden decrease in load. the pfc section also includes peak current limiting and input voltage brown- out protection. features n internally synchronized pfc and pwm in one ic n low start-up current (200a typ.) n low operating current (5.5ma typ.) n low total harmonic distortion n reduces ripple current in the storage capacitor between the pfc and pwm sections n average current continuous boost leading edge pfc n high efficiency trailing edge pwm optimized for current mode operation n current fed gain modulator for improved noise immunity n brown-out control, overvoltage protection, uvlo, and soft start block diagram 15 veao ieao v fb i ac v rms i sense ramp 1 oscillator ovp pfc i limit uvlo v ref pulse width modulator power factor corrector 2.5v + - - + 16 2 4 3 7.5v reference 14 v cc 13 v cc vea 8 + C iea 1 + - + - pfc out 12 s r q q s r q q 2.75v -1v ramp 2 9 pwm out 11 gnd 10 s r q q v dc 6 ss 5 r t c t 7 v cc duty cycle limit + - 1.5v - + 2.5v v fb - + 8v 8v v in ok gain modulator v cc 2 1.6k w 1.6k w 1.25v 25a - + dc i limit
ml4801 2 pin configuration pin description pin name function 9 ramp 2 pwm ramp current sense input 10 gnd ground 11 pwm out pwm driver output 12 pfc out pfc driver output 13 v cc positive supply (connected to an internal shunt regulator). 14 v ref buffered output for the internal 7.5v reference 15 v fb pfc transconductance voltage error amplifier input 16 veao pfc transconductance voltage error amplifier output pin name function 1 ieao pfc transconductance current error amplifier output 2i ac pfc gain control reference input 3i sense current sense input to the pfc current limit comparator 4v rms input for pfc rms line voltage compensation 5 ss connection point for the pwm soft start capacitor 6v dc pwm voltage feedback input 7r t c t connection for oscillator frequency setting components 8 ramp 1 pfc ramp input 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ieao i ac i sense v rms ss v dc r t c t ramp 1 veao v fb v ref v cc pfc out pwm out gnd ramp 2 top view ml4801 16-pin pdip (p16) 16-pin narrow soic (s16n)
ml4801 3 electrical characteristics unless otherwise specified, v cc = 15v, r t = 29.4k w , r ramp1 = 15.4k w , c t = 270pf, c ramp1 = 620pf, t a = operating temperature range (note 1) symbol parameter conditions min typ max units voltage error amplifier input voltage range 0 5 v transconductance v non inv = v inv , veao = 3.75v 40 65 80 w feedback reference voltage 2.43 2.50 2.57 v input bias current note 2 -0.5 -1.0 a output high voltage 6.0 6.7 v output low voltage 0.1 0.4 v source current d v in = 0.5v, v out = 6v -40 -70 -150 a sink current d v in = 0.5v, v out = 1.5v 40 70 150 a open loop gain 60 70 db psrr 11v < v cc < 16.5v 60 70 db current error amplifier input voltage range -1.5 2 v transconductance v non inv = v inv , veao = 3.75v 60 100 120 w input offset voltage 0 8 15 mv input bias current -0.5 -1.0 a output high voltage 6.0 6.7 v output low voltage 0.65 1.0 v source current d v in = 0.5v, v out = 6v -40 -70 -150 a sink current d v in = 0.5v, v out = 1.5v 40 70 150 a open loop gain 55 65 db psrr 11v < v cc < 16.5v 60 75 db absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. v cc ............................................................................................... 18v i sense voltage .................................................. -3v to 5v voltage on any other pin ...... gnd - 0.3v to v cc + 0.3v i ref ............................................................................................ 20ma i ac input current .................................................... 10ma peak pfc out current, source or sink ................ 500ma peak pwm out current, source or sink .............. 500ma pfc out, pwm out energy per cycle .................. 1.5j junction temperature .............................................. 150c storage temperature range ..................... C65c to 150c lead temperature (soldering, 10 sec) ..................... 260c thermal resistance ( q ja ) plastic dip ....................................................... 80c/w plastic soic .................................................. 105c/w operating conditions temperature range ml4801cx ................................................. 0c to 70c ml4801ix ............................................... -40c to 85c
ml4801 4 electrical characteristics (continued) symbol parameter conditions min typ max units ovp comparator threshold voltage 2.65 2.75 2.85 v hysteresis 175 250 325 mv pfc i limit comparator threshold voltage -0.9 -1.0 -1.1 v d pfc i limit threshold - gain modulator output 120 220 mv delay to output 150 300 ns dc i limit comparator threshold voltage 1.4 1.5 1.6 v input bias current 0.3 1 a delay to output 150 300 ns v in ok comparator threshold voltage 2.4 2.5 2.6 v hysteresis 0.8 1.0 1.2 v gain modulator gain (note 3) i ac = 100a, v rms = v fb = 0v 0.65 0.85 1.05 i ac = 50a, v rms = 1v, v fb = 0v 1.90 2.20 2.40 i ac = 50a, v rms = 1.8v, v fb = 0v 0.90 1.05 1.25 i ac = 100a, v rms = 3.3v, v fb = 0v 0.20 0.30 0.40 bandwidth iac = 100a 10 mhz output voltage i ac = 350a, v rms = 1v, 0.65 0.75 0.85 v v fb = 0v oscillator initial accuracy t a = 25oc 188 200 212 khz voltage stability 11v < v cc < 16.5v 1 % temperature stability 2% total variation over line and temp 182 218 khz ramp valley to peak voltage 2.5 v pfc dead time 350 470 600 ns c t discharge current v ramp 2 = 0v, v ramp 1 = 2.5v 3.5 5.5 7.5 ma
ml4801 5 electrical characteristics (continued) symbol parameter conditions min typ max units reference output voltage t a = 25oc, i(v ref ) = 1ma 7.4 7.5 7.6 v line regulation 11v < v cc < 16.5v 10 25 mv load regulation 1ma < i(v ref ) < 10ma 10 20 mv temperature stability 0.4 % total variation line, load, temp 7.35 7.65 v long term stability t j = 125oc, 1000 hours 5 25 mv pfc minimum duty cycle v ieao > 6.7v 0 % maximum duty cycle v ieao < 1.2v 90 95 % output low voltage i out = -20ma 0.4 0.8 v i out = -100ma 0.7 2.0 v i out = -10ma, v cc = 9v 0.4 0.8 v output high voltage i out = 20ma v cc - 0.8 v i out = 100ma v cc - 2.0 v rise/fall time c l = 1000pf 50 ns pwm dc duty cycle range 0-44 0-47 0-50 % v ol output low voltage i out = -20ma 0.4 0.8 v i out = -100ma 0.7 2.0 v i out = -10ma, v cc = 9v 0.4 0.8 v v oh output high voltage i out = 20ma v cc - 0. 8 v i out = 100ma v cc - 2.0 v rise/fall time c l = 1000pf 50 ns supply start-up current v cc = 12v, c l = 0 200 350 a operating current v cc = 14v, c l = 0 5.5 7.0 ma undervoltage lockout threshold 12.4 13.0 13.6 v undervoltage lockout hysteresis 2.7 3.0 3.3 v note 1: limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. note 2: includes all bias currents to other circuits connected to the v fb pin. note 3: gain = k x 5.3v; k = (i mulo - i offset ) x i ac x (veao - 0.625v) -1 .
ml4801 6 functional description the ml4801 consists of a combined average-current- controlled, continuous boost power factor corrector (pfc) front end and a synchronized pulse width modulator (pwm) back end. it is distinguished from earlier combo controllers by its dramatically reduced start-up and operating currents. the pwm section is intended to be used in current mode. the pwm stage uses conventional trailing-edge duty cycle modulation, while the pfc uses leading-edge modulation. this patented leading/trailing edge modulation technique results in a higher useable pfc error amplifier bandwidth, and can significantly reduce the size of the pfc dc buss capacitor. the synchronization of the pwm with the pfc simplifies the pwm compensation due to the reduced ripple on the pfc output capacitor (the pwm input capacitor). the pwm section of the ml4801 runs at twice the frequency of the pfc, which allows the use of smaller pwm output magnetics and filter capacitors while holding down the losses in the pfc stage power components. in addition to power factor correction, a number of protection features have been built into the ml4801. these include soft-start, pfc over-voltage protection, peak current limiting, brown-out protection, duty cycle limit, and under-voltage lockout. power factor correction power factor correction makes a non-linear load look like a resistive load to the ac line. for a resistor, the current drawn from the line is in phase with, and proportional to, the line voltage, so the power factor is unity (one). a common class of non-linear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. the peak- charging effect which occurs on the input filter capacitor in such a supply causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current in phase with the line voltage. such a supply presents a power factor to the line of less than one (another way to state this is that it causes significant current harmonics to appear at its input). if the input current drawn by such a supply (or any other non-linear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the ac line and a unity power factor will be achieved. to maintain the input current of a device drawing power from the ac line in phase with, and proportional to, the input voltage, a way must be found to cause that device to load the line in proportion to the instantaneous line voltage. the pfc section of the ml4801 uses a boost- mode dc-dc converter to accomplish this. the input to the converter is the full wave rectified ac line voltage. no filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges, at twice line frequency, from zero volts to the peak value of the ac input and back to zero. by forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current which the converter draws from the power line matches the instantaneous line voltage. one of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. a commonly used value is 385vdc, to allow for a high line of 270vac rms . the other condition is that the current which the converter is allowed to draw from the line at any given instant must be proportional to the line voltage. the first of these requirements is satisfied by establishing a suitable voltage control loop for the converter, which sets an average operating level for a current error amplifier and switching output driver. the second requirement is met by using the rectified ac line voltage to modulate the instantaneous input of the current control loop. such modulation causes the current error amplifier to command a power stage current which varies directly with the input voltage. in order to prevent ripple which will necessarily appear at the output of the boost circuit (typically about 10vac on a 385v dc level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. a final refinement is to adjust the overall gain of the pfc such to be proportional to 1/v in 2 , which linearizes the transfer function of the system as the ac input voltage varies. since the boost converter topology in the ml4801 pfc is of the current-averaging type, no slope compensation is required. pfc section gain modulator figure 1 shows a block diagram of the pfc section of the ml4801. the gain modulator is the heart of the pfc, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and pfc output voltage. there are three inputs to the gain modulator. these are: 1) a current representing the instantaneous input voltage (amplitude and waveshape) to the pfc. the rectified ac input sine wave is converted to a proportional current via an (external) resistor and is then fed into the gain modulator at i ac . sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. the gain modulator responds linearly to this current. 2) a voltage proportional to the long-term rms ac line voltage, derived from the rectified line voltage after scaling and filtering. this signal is presented to the gain modulator at v rms . the gain modulators output is
ml4801 7 inversely proportional to v rms 2 (except at unusually low values of v rms where special gain contouring takes over to limit power dissipation of the circuit components under heavy brownout conditions). the relationship between v rms and gain is designated as k. 3) the output of the voltage error amplifier, veao. the gain modulator responds linearly to variations in this voltage. the output of the gain modulator is a current signal, in the form of a full wave rectified sinusoid at twice the line frequency. this current is applied to the virtual-ground (negative) input of the current error amplifier. in this way the gain modulator forms the reference for the current error loop, and ultimately controls the instantaneous current draw of the pfc from the power line. the general form for the output of the gain modulator is: i iveao v v gainmod ac rms = 2 1 more exactly, the output current of the gain modulator is given by: i k veao v i gainmod ac = - (.) 0625 (1) where k is in units of v -1 . note that the output current of the gain modulator is limited to @ 500a. current error amplifier the current error amplifiers output controls the pfc duty cycle to keep the current through the boost inductor a linear function of the line voltage. at the inverting input to the current error amplifier, the output current of the gain modulator is summed with a current which results from a negative voltage being impressed upon the i sense pin (current into i sense @ v sense /1.6k w) . the negative voltage on i sense represents the sum of all currents flowing in the pfc circuit, and is typically derived from a current sense resistor in series with the negative terminal of the input bridge rectifier. in higher power applications, two current transformers are sometimes used, one to monitor the i d of the boost mosfet(s) and one to monitor the i f of the boost diode. as stated above, the inverting input of the current error amplifier is a virtual ground. given this fact, and the arrangement of the duty cycle modulator polarities internal to the pfc, an increase in positive current from the gain modulator will cause the output stage to increase its duty cycle until the voltage on i sense is adequately negative to cancel this increased current. similarly, if the gain modulators output decreases, the output duty cycle will decrease to achieve a less negative voltage on the i sense pin. cycle-by-cycle current limiter the i sense pin, as well as being a part of the current feedback loop, is a direct input to the cycle-by-cycle current limiter for the pfc section. should the input voltage at this pin ever be more negative than -1v, the output of the pfc will be disabled until the protection flip-flop is reset by the clock pulse at the start of the next pfc power cycle. functional description (continued) 15 veao ieao v fb i ac v rms i sense ramp 1 oscillator ovp pfc i limit v ref power factor corrector 2.5v + - - + 16 2 4 3 7.5v reference 14 v cc 13 vea 8 + C iea 1 + - pfc out 12 2.75v -1v r t c t 7 gain modulator 2 1.6k w 1.6k w 8v pfc output driver pfc controller duty cycle limit figure 1. pfc section block diagram
ml4801 8 overvoltage protection the ovp comparator serves to protect the power circuit from being subjected to excessive voltages if the load should suddenly change. a resistor divider from the high voltage dc output of the pfc is fed to v fb . when the voltage on v fb exceeds 2.75v, the pfc output driver is shut down. the pwm section will continue to operate. the ovp comparator has 250mv of hysteresis, and the pfc will not restart until the voltage at v fb drops below 2.5v. the ovp trip level should be set at a level where the active and passive external power components and the ml4801 are within their safe operating voltages, but not so low as to interfere with the regulator operation of the boost voltage regulation loop. error amplifier compensation the pwm loading of the pfc can be modeled as a negative resistor; an increase in input voltage to the pwm causes a decrease in the input current. this response dictates the proper compensation of the two transconductance error amplifiers. figure 2 shows the types of compensation networks most commonly used for the voltage and current error amplifiers, along with their respective return points. the current loop compensation is returned to v ref to produce a soft-start characteristic on the pfc: as the reference voltage comes up from zero volts, it creates a differentiated voltage on ieao which prevents the pfc from immediately demanding a full duty cycle on its boost converter. there are two major concerns when compensating the voltage loop error amplifier; stability and transient response. optimizing interaction between transient response and stability requires that the error amplifiers open-loop crossover frequency should be 1/2 that of the line frequency, or 23hz for a 47hz line (lowest anticipated international power frequency). rapid perturbations in line or load conditions will cause the input to the voltage error amplifier (v fb ) to deviate from its 2.5v (nominal) value. if this happens, the transconductance of the voltage error amplifier will increase significantly. this increases the gain-bandwidth product of the voltage loop, resulting in a much more rapid voltage loop response to such perturbations than would occur with a conventional linear gain characteristic. the current amplifier compensation is similar to that of the voltage error amplifier with the exception of the choice of crossover frequency. the crossover frequency of the current amplifier should be at least 10 times that of the voltage amplifier, to prevent interaction with the voltage loop. it should also be limited to less than 1/6th that of the switching frequency, e.g. 16.7khz for a 100khz switching frequency. there is a also a degree of gain contouring applied to the transfer characteristic of the current error amplifier, to increase its speed of response to current-loop perturbations. however, the boost inductor will usually be the dominant factor in overall current loop response. therefore, this contouring is significantly less marked than that of the voltage error amplifier. for more information on compensating the current and voltage control loops, see application notes 33, 34, and 55. application note 16 also contains valuable information for the design of this class of pfc. oscillator (r t c t ) the oscillator frequency is set by the values of r t and c t , which determine the ramp and off-time of the ml4801's master oscillator: f tt osc ramp deadtime = + 1 (2) the deadtime of the oscillator is derived from the following equation: tcr v v ramp t t ref ref = - - f h g i k j ln . . 125 375 (3) at v ref = 7.5v: tcr ramp t t = 051 . the ramp of the oscillator may be determined using: t v ma cc deadtime t t == 25 55 455 . . (4) the deadtime is so small (t ramp >> t deadtime ) that the functional description (continued) 15 veao ieao v fb i ac v rms i sense 2.5v - + 16 2 4 3 vea - + iea + - gnd v ref 1 pfc output gain modulator figure 2. compensation network connections for the voltage and current error amplifiers
ml4801 9 operating frequency can typically be approximated by: f t osc ramp = 1 (5) example: for the application circuit shown in the data sheet, with the oscillator running at: fkhz t osc ramp == 100 1 trc ramp t t == - 051 1 10 5 . solving for r t x c t yields 2 x 10 -4 . selecting standard components values, c t = 270pf, and r t = 36.5k w . pwm section the pwm section of the ml4801 is straightforward, but there are several points which should be noted. foremost among these is its inherent synchronization to the pfc section of the device, and that the pwm stage is optimized for current-mode operation. in the ml4801, the operating frequency of the pfc section is fixed at 1/2 of the pwm's operating frequency. this is done through the use of a 2:1 digital frequency divider ("t" flip-flop) linking the two functional sections of the ic. no voltage error amplifier is included in the pwm stage of the ml4801, as this function is generally performed on the output side of the pwms isolation boundary. to facilitate the design of optocoupler feedback circuitry, an offset has been built into the pwms ramp 2 input which allows v dc to command a zero percent duty cycle for input voltages below 1.25v. pwm current limit the ramp 2 pin provides a direct input to the cycle-by- cycle current limiter for the pwm section. should the input voltage at this pin ever exceed 1.5v, the output of the pwm will be disabled until the output flip-flop is reset by the clock pulse at the start of the next pwm power cycle. v in ok comparator the v in ok comparator monitors the dc output of the pfc and inhibits the pwm if this voltage on v fb is less than its nominal 2.5v. once this voltage reaches 2.5v, which corresponds to the pfc output capacitor being charged to its rated boost voltage, the soft-start commences. pwm control (ramp 2) in addition to its pwm current limit function, ramp 2 is used as the sampling point for a voltage representing the current in the primary of the pwms output transformer. this voltage may be derived either by a current sensing resistor or a current transformer. soft start start-up of the pwm is controlled by the selection of the external capacitor at ss. a current source of 25a supplies the charging current for the capacitor, and start- up of the pwm begins at 1.25v. start-up delay can be programmed by the following equation: ct a v ss delay = 25 125 m . (6) where c ss is the required soft start capacitance, and t delay is the desired start-up delay. it is important that the time constant of the pwm soft-start allow the pfc time to generate sufficient output power for the pwm section. the pwm start-up delay should be at least 5ms. solving for the minimum value of c ss : cms a v nf ss = = 5 25 125 100 m . generating v cc the ml4801 is a voltage-fed part. it requires an external 15v10% or better zener shunt voltage regulator, or some other v cc regulator, to maintain the voltage supplied to the part at 15v nominal. this allows a low power dissipation while at the same time delivering 13v nominal of gate drive at the pwm out and pfc out outputs. if using a zener diode, it is important to limit the current through the zener to avoid overheating or destroying it. this can be easily done with a single resistor in series with the vcc pin, returned to a bias supply of typically 18v to 20v. the resistors value must be chosen to meet the operating current requirement of the ml4801 itself (8.5ma max.) plus the current required by the two gate driver outputs. example: with a v bias of 20v, a v cc limit of 16.5v (max) and driving a total gate charge of 110nc at 100khz (1 irf840 mosfet and 2 irf830 mosfets), the gate driver current required is: ikhzncma gatedrive == 100 110 11 r vv ma ma bias = - + = 20 16 5 75 11 180 . . w the ml4801 should be locally bypassed with a 10nf and a 1 m f ceramic capacitor. in most applications, an electrolytic capacitor of between 33f and 100f is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. functional description (continued)
ml4801 10 leading/trailing modulation conventional pulse width modulation (pwm) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. the error amplifier output voltage is then compared with the modulating ramp. when the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned off. when the switch is on, the inductor current will ramp up. the effective duty cycle of the trailing edge modulation is determined during the on time of the switch. figure 3 shows a typical trailing edge control scheme. in the case of leading edge modulation, the switch is turned off right at the leading edge of the system clock. when the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned on. the effective duty-cycle of the leading edge modulation is determined during the off time of the switch. figure 4 shows a leading edge control scheme. one of the advantages of this control technique is that it requires only one system clock. switch 1 (sw1) turns off and switch 2 (sw2) turns on at the same instant to minimize the momentary no-load period, thus lowering ripple voltage generated by the switching action. with such synchronized switching, the ripple voltage of the first stage is reduced. calculation and evaluation have shown that the 120hz component of the pfcs output ripple voltage can be reduced by as much as 30% using this method. typical applications figure 9 is the application circuit for a complete 100w power factor corrected power supply, designed using the methods and general topology detailed in application note 33. ref ea C + C + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 veao cmp u2 ramp veao time vsw1 time figure 4. leading/trailing edge control scheme figure 3. typical trailing edge control scheme ramp veao time vsw1 time ref ea C + C + osc dff r d q q clk u1 ramp clk u4 u3 c1 rl i4 sw2 sw1 + dc i1 i2 i3 vin l1 u2
ml4801 11 figure 5. i veao vs. v fb figure 6. g m of v ota figure 7. g m of i ota figure 8. k of multiplier 160 0 C160 i veao (a) v fb (v) 024 5 13 180 90 0 s v fb (v) 024 5 13 200 160 120 80 40 0 s v fb (v) 024 5 13 500 0 k v rms (v) 024 5 13
ml4801 12 figure 9. 100w power factor corrected power supply ac input 85 to 265vac c1 680nf ml4801 f1 3.15a r5 300m w 1w br1 4a, 600v d12 1n5401 d13 1n5401 r2a 357k w r2b 357k w r3 75k w r4 13k w r1a 249k w r1b 249k w r12 27k w c6 1f c7 220pf r11 768k w c19 220nf c2 470nf r27 82k w c18 270pf r6 36.5k w r10 6.2k w 20k w 60k w 470pf c11 10nf c3 100nf c30 47f r21 22 w 15v c4 10nf c5 100f r14 33 w d10 1n5818 d8 1n5818 r7a 178k w r7b 178k w c12 20f 1n4745 16v d3 byv26c q1 irf840 q2 irf830 c13 100nf c14 1f ieao i ac i sense v rms ss v dc rtct ramp 1 vdc v fb v ref v cc pfc out pwm out gnd ramp 2 q3 irf830 r15 3 w c20 1f r28 180 w 12vdc l2 15h l1 3mh c21 1800f c24 1f rtn d11 mbr2545ct d5 byv26c d6 byv26c c25 100nf r17 33 w r30 4.7k w d7 16v r22 8.66k w r25 2.26k w r20 1.5 w c15 10nf c16 1f c31 1nf r8 2.37k w c8 100nf c9 10nf c17 220pf r19 220 w r23 1.5k w 10k w r24 1.2k w c22 4.7f tl431 r26 10k w c23 100nf r18 220 w t2 t1 l1: premier magnetics #tsd-734 l2: 15h, 10a dc t1: premier magnetics #pmgd- 03 t2: premier magnetics #tsd-1048 premier magnetics: (714) 362-4211 d1 8a, 600v "fred " diode 1nf
ml4801 15 physical dimensions inches (millimeters) seating plane 0.240 - 0.260 (6.09 - 6.61) pin 1 id 0.295 - 0.325 (7.49 - 8.26) 0.740 - 0.760 (18.79 - 19.31) 0.016 - 0.022 (0.40 - 0.56) 0.100 bsc (2.54 bsc) 0.008 - 0.012 (0.20 - 0.31) 0.015 min (0.38 min) 16 0o - 15o 1 0.055 - 0.065 (1.40 - 1.65) 0.170 max (4.32 max) 0.125 min (3.18 min) 0.02 min (0.50 min) (4 places) package: p16 16-pin pdip seating plane 0.148 - 0.158 (3.76 - 4.01) pin 1 id 0.228 - 0.244 (5.79 - 6.20) 0.386 - 0.396 (9.80 - 10.06) 0.012 - 0.020 (0.30 - 0.51) 0.050 bsc (1.27 bsc) 0.015 - 0.035 (0.38 - 0.89) 0.059 - 0.069 (1.49 - 1.75) 0.004 - 0.010 (0.10 - 0.26) 0.055 - 0.061 (1.40 - 1.55) 16 0.006 - 0.010 (0.15 - 0.26) 0o - 8o 1 0.017 - 0.027 (0.43 - 0.69) (4 places) package: s16n 16-pin narrow soic
ml4801 1 4 ds 48 01 -01 part number temperature range package ML4801CP 0c to 70c 16-pin plastic dip (p16) ml4801cs 0c to 70c 16-pin narrow soic (s16n) ml4801ip C40c to 85c 16-pin plastic dip (p16) ml4801is C40c to 85c 16-pin narrow soic (s16n) ordering information 2092 concourse drive san jose, ca 95131 tel: (408) 433-5200 fax: (408) 432-0295 www.microlinear.com ? micro linear 1998. is a registered trademark of micro linear corporation. all other trademarks are the property of their respective owners. products described herein may be covered by one or more of the following u.s. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723. japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. other patents are pending. micro linear reserves the right to make changes to any product herein to improve reliability, function or design. micro linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. the circuits contained in this data sheet are offered as possible applications only. micro linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. the customer is urged to consult with appropriate legal counsel before deciding on a particular application.

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